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? semiconductor components industries, llc, 2004 august, 2004 ? rev. 1 1 publication order number: eclsoic8evb/d eclsoic8evb evaluation board manual for high frequency soic 8 introduction on semiconductor has developed an evaluation board for the devices in 8?lead soic package. these evaluation boards are offered as a convenience for the customers interested in performing their own engineering assessment on the general performance of the 8?lead soic device samples. the board provides a high bandwidth 50 controlled impedance environment. the pictures in figure 1 show the top and bottom view of the evaluation board, which can be configured in several different ways, depending on device under test (see table 1. configuration list). this evaluation board manual contains: ? information on 8?lead soic evaluation board ? assembly instructions ? appropriate lab setup ? bill of materials this manual should be used in conjunction with the device data sheet, which contains full technical details on the device specifications and operation. board lay?up the 8?lead soic evaluation board is implemented in four layers with split (dual) power supplies (figure 2. evaluation board lay?up). for standard ecl lab setup and test, a split (dual) power supply is essential to enable the 50 internal impedance in the oscilloscope as a termination for ecl devices. the first layer or primary trace layer is 0.008 thick rogers ro4003 material, which is designed to have equal electrical length on all signal traces from the device under the test (dut) to the sense output. the second layer is the 1.0 oz copper ground plane and a portion of the plane is the v ee power plane. the fr4 dielectric material is placed between second and third layer and between third and fourth layer. the third layer is also 1.0 oz copper ground plane and a portion of this layer is v cc power plane. the fourth layer is the secondary trace layer. figure 1. top and bottom view of the 8?lead soic evaluation board evaluation board manual http://onsemi.com
eclsoic8evb http://onsemi.com 2 figure 2. evaluation board lay?up lay?up detail 4 layer layer 1 (top side) rogers 4003 0.008 in layer 2 (ground and vee plane p1) 1 oz fr?4 0.020 in layer 3 (ground and vcc plane p2) 1 oz fr?4 0.025 in layer 4 (bottom side) silkscreen (top side) 0.062 0.007 board layout the 8?lead soic evaluation board was designed to be versatile and accommodate several different configurations. the input, output, and power pin layout of the evaluation board is shown in figure 3. the evaluation board has at least eleven possible configurable options. table 1. list the devices and the relevant configuration that utilizes this pcb board. list of components and simple schematics are located in figures 4 through 14. place sma connectors on j1 through j7, 50 chip resistors on r1 through r7, and chip capacitors c1 through c4 according to configuration figures. (c1 and c2 are 0.01 f and c3 and c4 are 0.1 f). figure 3. evaluation board layout top view bottom view
eclsoic8evb http://onsemi.com 3 table 1. configuration list eclinps lite device comments configuration mc10el01d/mc100el01d see figure 4 1 mc10el04d/mc100el04d see figure 5 2 mc10el05d/mc100el05d see figure 4 1 mc10el07d/mc100el07d see figure 5 2 mc10el11d/mc100el11d see figure 6 3 mc10el12d/mc100el12d see figure 6 3 mc10el16d/mc100el16d* see figure 5 2 mc10el31d/mc100el31d see figure 4 1 mc10el32d/mc100el32d see figure 7 4 mc10el33d/mc100el33d see figure 7 4 mc10el35d/mc100el35d see figure 4 1 mc10el51d/mc100el51d see figure 4 1 mc10el52d/mc100el52d see figure 4 1 mc10el58d/mc100el58d see figure 8 5 mc10el89d/mc100el89d see figure 6 3 mc10elt20d/ mc100elt20d see figure 9 6 mc10elt21d/ mc100elt21d see figure 10 7 mc10elt22d/ mc100elt22d see figure 11 8 mc100elt23d see figure 12 9 mc10elt26d/ mc100elt26d see figure 13 10 mc10elt28d/ mc100elt28d see figure 14 11 low voltage eclinps device comments configuration mc100lvel01d see figure 4 1 mc100lvel05d see figure 4 1 mc100lvel11d see figure 6 3 mc100lvel12d see figure 6 3 mc100lvel16d* see figure 5 2 mc100lvel31d see figure 4 1 mc100lvel32d see figure 7 4 mc100lvel33d see figure 7 4 mc100lvel51d see figure 4 1 mc100lvel58d see figure 8 5 mc100lvelt22d see figure 11 8 mc100lvelt23d see figure 12 9 eclinps plus device comments configuration mc10ep01d/mc100ep01d see figure 4 1 mc10ep05d/mc100ep05d see figure 4 1 mc10ep08d/mc100ep08d see figure 4 1 mc10ep11d/mc100ep11d see figure 6 3 mc10ep16d/ mc100ep16d* see figure 5 2 mc100ep16fd* see figure 5 2 mc10ep16td/ mc100ep16td* see figure 5 2 mc100ep16vad* see figure 5 2 mc100ep16vbd* see figure 5 2 mc100ep16vcd* see figure 8 5 mc100ep16vsd* see figure 5 2 mc100ep16vtd* see figure 5 2 mc10ep31d/mc100ep31d see figure 4 1 mc10ep32d/mc100ep32d see figure 7 4 mc10ep33d/mc100ep33d see figure 7 4 mc10ep35d/MC100EP35D see figure 4 1 mc10ep51d/mc100ep51d see figure 4 1 mc10ep52d/mc100ep52d see figure 4 1 mc10ep58d/mc100ep58d see figure 8 5 mc100ep89d see figure 6 3 mc10ept20d/ mc100ept20d see figure 9 6 mc100ept21d* see figure 10 7 mc100ept22d see figure 11 8 mc100ept23d* see figure 12 9 mc100ept26d* see figure 13 10 low voltage eclinps plus device comments configuration mc100lvep11d see figure 6 3 mc100lvep16d* see figure 5 2 *see appendix for additions or modifications to the current configuration. eclinps max device comments configuration nb6l11d see figure 6 3 nb6l16d see figure 5 2
eclsoic8evb http://onsemi.com 4 evaluation board assembly instructions the 8?lead soic evaluation board is designed for characterizing devices in a 50 laboratory environment using high bandwidth equipment. each signal trace on the board has a via, which has an option of termination resistor or bypassing capacitor depending on the input/output configuration (see table 1. configuration list). table 17 contains the bill of materials for this evaluation board. solder the device on the evaluation board the soldering can be accomplished by hand soldering or soldering re?flow techniques. make sure pin 1 of the device is located next the white dotted mark u1 and all the pins are aligned to the footprint pads. solder the 8?lead soic device to the evaluation board. connecting power and ground planes for standard ecl lab setup and test, a split (dual) power supply is required enabling the 50 internal impedance in the oscilloscope to be used as a termination of the ecl signals (v tt = v cc 2.0 v, in split power supply setup, v tt is the system ground, v cc is 2.0 v, and v ee is 3.0 v or 1.3 v; see table 2: power supply levels). table 2. power supply levels power supply v cc v ee gnd 5.0 v 2.0 v ?3.0 v 0.0 v 3.3 v 2.0 v ?1.3 v 0.0 v 2.5 v 2.0 v ?0.5 v 0.0 v the power supply for voltage level translating device need slight modification as indicated in table 3. power supply levels for translators. table 3. power supply levels for translators v cc v ee gnd pecl translators 3.3 v / 5.0 v 0.0 v 0.0 v on the top side of the evaluation board solder the four surface mount test point clips to the pads labeled v cc , v ee , and gnd. the v cc clip connects directly to pin 8 of the device. the v ee clip connects directly to pin 5 of the device. there are two gnd clip footprints which can be connected to the ground plane of the evaluation board depending on the setup configuration. it is recommended to solder 0.01 f capacitors to c1 and c2 to reduce the unwanted noise from the power supplies. c3 and c4 pads are provided for 0.1 f capacitor to further diminish the noise from the power supplies. adding capacitors can improve edge rates, reduce overshoot and undershoot. termination all ecl outputs need to be terminated to v tt (v tt = v cc 2.0 v = gnd) via a 50 resistor in a split power supply lab set?up. 0603 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ecl driver (more information on termination is provided in an8020). s older the chip resistors to the bottom side of the board on the appropriate input of the device pins labeled r1, r2, r3, r4, r6, and r7, depending on the specific device. installing the sma connectors each configuration indicates the number of sma connectors needed to populate an evaluation board for a given configuration. each input and output requires one sma connector. attach all the required sma connectors onto the board and solder the connectors to the board. please note that alignment of the signal connector pin of the sma can influence the lab results. the reflection and launch of the signals are largely influenced by imperfect alignment and soldering of the sma connector. validating the assembled board after assembling the evaluation board, it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process. time domain reflectometry (tdr) is another highly recommended validation test.
eclsoic8evb http://onsemi.com 5 configurations j1 j3 j4 j2 r1 50 r2 50 r3 50 r4 50 j5 j6 c1 0.01 f gnd c4 0.1 f c2 0.01 f gnd c3 0.1 f figure 4. configuration 1 schematic v cc v ee dut table 4. configuration 1 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10el01d/mc100el01d mc10el05d/mc100el05d mc10el31d/mc100el31d mc10el35d/mc100el35d mc10el51d/mc100el51d mc10el52d/mc100el52d mc100lvel01d mc100lvel05d mc100lvel31d yes yes yes yes yes yes yes yes yes yes yes no yes no yes yes mc100lvel51d mc10ep01d/mc100ep01d mc10ep05d/mc100ep05d mc10ep08d/mc100ep08d mc10ep31d/mc100ep31d mc10ep35d/MC100EP35D mc10ep51d/mc100ep51d mc10ep52d/mc100ep52d
eclsoic8evb http://onsemi.com 6 j3 j4 j2 r2 50 r3 50 j7 j6 c1 0.01 f gnd c4 0.1 f c2 0.01 f gnd c3 0.1 f v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 figure 5. configuration 2 schematic (optional) table 5. configuration 2 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10el04d/mc100el04d mc10el07d/mc100el07d mc10el16d/mc100el16d* mc100lvel16d* mc10ep16d/mc100ep16d* mc100ep16fd* mc100lvep160* no no yes yes yes yes no no yes yes yes no yes no yes yes mc10ep16td/mc100ep16td* mc100ep16vad* mc100ep16vbd* mc100ep16vsd* mc100ep16vtd* nb6l160d *see appendix for additional or modification to the current configuration
eclsoic8evb http://onsemi.com 7 j3 j4 j2 r7 50 j7 j6 c1 0.01 f gnd c4 0.1 f c2 0.01 f gnd c3 0.1 f v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 j1 figure 6. configuration 3 schematic r6 50 table 6. configuration 3 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10el11d/mc100el11d mc10el12d/mc100el12d mc10el89d/mc100el89d mc100lvel11d mc100lvel12d yes no yes no yes no yes no yes yes yes yes yes yes yes yes mc10ep11d/mc100ep11d mc100ep89d mc100lvep11d nb6l11d
eclsoic8evb http://onsemi.com 8 j1 j3 j4 j2 r3 50 j7 j6 c1 0.01 f gnd c4 0.1 f c2 0.01 f gnd c3 0.1 f v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 (optional) figure 7. configuration 4 schematic r2 50 r1 50 table 7. configuration 4 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10el32d/mc100el32d mc10el33d/mc100el33d mc100lvel32d yes yes yes yes yes yes no no yes yes yes no yes no yes yes mc100lvel33d yes yes yes yes yes yes no no yes yes yes no yes no yes yes mc10ep32d/mc100ep32d mc10ep33d/mc100ep33d
eclsoic8evb http://onsemi.com 9 j3 j4 j2 r4 50 j7 j6 c1 0.01 f gnd c4 0.1 f c2 0.01 f gnd c3 0.1 f v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 (optional) figure 8. configuration 5 schematic r3 50 r2 50 table 8. configuration 5 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc100ep16vcd* mc10el58d/mc100el58d no no yes yes yes yes yes yes yes yes yes no yes no yes yes mc100lvel58d no no yes yes yes yes yes yes yes yes yes no yes no yes yes mc10ep58d/mc100ep58d *see appendix for addition or modification to the current configuration
eclsoic8evb http://onsemi.com 10 j3 j2 r7 50 (optional) j7 c1 0.01 f gnd c4 0.1 f gnd short v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 figure 9. configuration 6 ? translator schematic table 9. configuration 6 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10elt20d/mc100el20d no no yes no yes no no no no no no no yes o p tional yes yes mc10ept20d/mc100ept20d no no yes no yes no no no no no no no yes optional yes yes
eclsoic8evb http://onsemi.com 11 j3 j2 r3 50 j7 c1 0.01 f gnd c4 0.1 f gnd short v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 figure 10. configuration 7 ? translator schematic (unloaded testing condition) r2 50 table 10. configuration 7 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10elt21d/mc100el21d no no yes yes yes yes no no no no no no yes no yes yes mc100ept21d n o n o y es y es y es y es n o n o n o n o n o n o y es n o y es y es *see appendix for loaded testing condition.
eclsoic8evb http://onsemi.com 12 j3 j2 r6 50 (optional) j7 c1 0.01 f gnd c4 0.1 f gnd short v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 figure 11. configuration 8 ? translator schematic j6 j4 j1 r7 50 (optional) table 11. configuration 8 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j57 r7 c1 c4 mc10elt22d/ mc100el22d y n y n y n y n n n y oti l y oti l y y mc100lvelt22d yes no yes no yes no yes no no no yes optional yes optional yes yes mc100ept22d
eclsoic8evb http://onsemi.com 13 j3 j2 j7 c1 0.01 f gnd c4 0.1 f gnd short v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 j6 j4 j1 figure 12. configuration 9 ? translator schematic (unloaded testing condition) r1 50 r2 50 r3 50 r4 50 table 12. configuration 9 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc100el23d y mc100lvelt23d yes yes yes yes yes yes yes yes no no yes no yes no yes yes mc100ept23d *see appendix for loaded testing condition.
eclsoic8evb http://onsemi.com 14 j3 j2 j7 c1 0.01 f gnd c4 0.1 f gnd short v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 r2 50 j6 figure 13. configuration 10 ? translator schematic (unloaded testing condition) r3 50 table 13. configuration 10 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10elt26d/mc100elt26d no no yes yes yes yes no no no no yes yes yes no yes yes mc100ept26d n o n o y es y es y es y es n o n o n o n o y es y es yes n o yes yes *see appendix for loaded testing condition.
eclsoic8evb http://onsemi.com 15 j3 j2 r6 50 (optional) j7 c1 0.01 f gnd c4 0.1 f gnd short v cc v ee dut pin 4 pin 3 pin 2 pin 1 pin 5 pin 6 pin 7 pin 8 j6 figure 14. configuration 11 ? translator schematic j2 j3 r1 50 r2 50 table 14. configuration 11 pin 1 pin 2 pin 3 pin 4 pin 5 pin 6 pin 7 pin 8 device j1 r1 j2 r2 j3 r3 j4 r4 c2 c3 j6 r6 j7 r7 c1 c4 mc10elt28d/mc100elt28d yes yes yes yes yes no yes no no no yes optional yes no yes yes
eclsoic8evb http://onsemi.com 16 lab setup figure 15. example of standard lab setup (configuration 1) out2 channel 1 channel 2 out1 trigger trigger differential signal generator v ee out1 out2 gnd power supply v cc gnd power supply test measuring equipment j1 j2 j3 j4 j6 j7 dut 1. connect appropriate power supplies to v cc , v ee , and gnd. for standard ecl lab setup and test, a split (dual) power supply is required enabling the 50 internal impedance in the oscilloscope to be used as a termination of the ecl signals (v tt = v cc 2.0 v, in split power supply setup, v tt is the system ground, v cc is 2.0 v, and v ee is 3.0 v or 1.3 v; see table 15). table 15. power supply levels power supply v cc v ee gnd 5.0 v 2.0 v ?3.0 v 0.0 v 3.3 v 2.0 v ?1.3 v 0.0 v 2.5 v 2.0 v ?0.5 v 0.0 v the power supply for voltage level translating device need slight modification as indicated in table 16. table 16. power supply levels for translators v cc v ee gnd pecl translators 3.3 v / 5.0 v 0.0 v 0.0 v 2. connect a signal generator to the input sma connectors. setup input signal according to the device data sheet. 3. connect a test measurement device on the device output sma connectors. note: the test measurement device must contain 50 termination.
eclsoic8evb http://onsemi.com 17 table 17. bill of materials components manufacturer description part number web site sma connector rosenberger sma connector, side launch, gold plated 32k243?40me3 http://www.rosenberger.de http://www.rosenbergerna.com johnson components* sma connector, side launch, gold plated 142?0701?851 http://www.johnsoncomponents.com surface mount test points keystone* smt miniature test point 5015 http://www.keyelco.com points smt compact test point 5016 thru?hole mount compact test point 5005?5009 chip capacitor avc corporation* 0603 0.01 f 10% 06035c103kat2a http://www.avxcorp.com 0603 0.1 f 10% 06035c104kat2a chip resistor vishay dale* 0603 50 1% thick film resistor crcw060351r1j http://www.vishay.com evaluation board on semiconductor soic 8 evaluation board eclsoic8evb http://www.onsemi.com device samples on semiconductor soic 8 package device various http://www.onsemi.com *components are available through most distributors, i.e. www.newark.com, www.digikey.com
eclsoic8evb http://onsemi.com 18 appendix a (modified configurations) mc10el16d/mc100el16d mc100lvel16d mc10ep16d/mc100ep16d mc10ep16df/mc100ep16df mc100ep16vad mc100lvep16d the devices listed above have the option of being driven single?endedly by using the provided v bb pin of the device. in order to drive it single?endedly, configuration 2 needs to be modified. 1. remove the 50 chip resistor from r3. 2. short pin 3 and pin 4 together. option a) short r3 and r4 trace pads. or option b) place a sma connector on j4 and use a cable with sma connectors to short j3 and j4 connectors. mc10ep16d/mc100ep16dt this device has an option of being 50 terminated internally. to evaluate the internal 50 resistor of the device, configuration 2 needs to be modified. 1. remove the 50 chip resistors from r2 and r3. 2. short r1 and r4 to v tt (gnd). option a) short r1 and r4 to v tt (gnd). or option b) place sma connectors on j1 and j4. place shorting barrels on j1 and j4 sma connector. mc100ep16vbd this device has an option of single?ended feedback output and being driven single?endedly using the v bb . to utilize the feedback option and drive it single?endedly, configuration 2 needs to be modified. feedback option 1. connect a sma connector on j1 drive single?endedly 2. remove the 50 chip resistor from r3. 3. short pin 3 and pin 4 together. option a) short r3 and r4. or option b) place a sma connector on j4 and use a cable with sma connectors to short j3 and j4 connectors. mc100ep16vcd this device has an option of single?ended feedback output with an enable pin. to utilize the feedback option and enable option, configuration 5 needs to be modified. 1. connect a sma connector on j1. 2. remove the 50 chip resistor from r3. mc100ep16vsd this device has an option of varying the output swing amplitude and being driven single?endedly. in order to utilize these options, configuration 2 needs to be modified. output swing control 1. connect a sma connector on j1 2. add a decoupling capacitor between j1 and v cc (0.01 f) drive single?endedly 1. remove the 50 chip resistor from r3. 2. short pin 3 and pin 4 together. option a) short r3 and r4. or option b) place a sma connector on j4 and use a cable with sma connectors to short j3 and j4 connectors. mc100ep16vtd this device has an option of varying the output swing amplitude and internal termination. in order to utilize these options, configuration 2 needs to be modified. output swing control 1. connect a sma connector on j1 2. add a decoupling capacitor between j1 and v cc (0.0 1 f) internal termination 1. remove the 50 chip resistors from r2 and r3. 2. short r1 and r4 to v tt (gnd) option a) short r1 and r4 to v tt (gnd). or option b) place sma connectors on j1 and j4. place shorting barrels on j1 and j4 sma connector. mc10elt21d/mc100el21d mc100el23d mc10elt26d/mc100elt26d mc100ept21d mc100ept23d mc100ept26d mc100lvelt23 the ttl output data presented in the data sheet are obtained under 500 load resistor in parallel with 20 pf fixture capacitance. in order to obtain comparable data as in the data sheet, the evaluation board needs to be modified. 1. cut the output trace so that the 0402* size chip resistor can be placed over the cut out trace. 2. solder a 450 chip resistor across the cut out trace. *any size chip resistor can be used. the recommended size of the chip resistor is 0402, to reduce the effect of parasitic with a 17 mil trace width. 450 in series with 50 instrument resistance add up to 500 loaded condition.
eclsoic8evb http://onsemi.com 19 appendix b (gerber files) top layer second layer (v ee and ground plane third layer (v cc and ground plane) figure 16. gerber files bottom layer
eclsoic8evb http://onsemi.com 20 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 eclsoic8evb/d eclinps, eclinps lite, eclinps plus, and eclinps max are trademarks of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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